Publications

IMPORTANT INFORMATION

Any usage of VirtualSoC for research, commercial or other purposes must be properly acknowledged in the resulting products or publications. Specifically, the publications 1 and 2 below must be cited in all cases.

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  1. Bortolotti, Daniele, Christian Pinto, Andrea Marongiu, Martino Ruggiero, and Luca Benini. “VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip.” In IPDPS Workshops, pp. 2182-2187. 2013.
  2. Bortolotti, Daniele, Francesco Paterna, Christian Pinto, Andrea Marongiu, Martino Ruggiero, and Luca Benini. “Exploring instruction caching strategies for tightly-coupled shared-memory clusters.” In System on Chip (SoC), 2011 International Symposium on, pp. 34-41. IEEE, 2011.

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List of papers related to VirtualSoC

    • Rahimi, A., Marongiu, A., Burgio, P., Gupta, R. K., & Benini, L. (2013, March). Variation-tolerant OpenMP tasking on tightly-coupled processor clusters. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 (pp. 541-546). IEEE.
    • Rahimi, A., Benini, L., & Gupta, R. (2012, July). Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters. In Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (pp. 415-420). ACM.
    • Burgio, P., Tagliavini, G., Marongiu, A., & Benini, L. (2013, March). Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 (pp. 1504-1509). IEEE.
    • Papagiannopoulou, D., Bahar, R., Moreshet, T., Herlihy, M., Marongiu, A., & Benini, L. (2013, June). Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. In Proceedings of the First International Workshop on Many-core Embedded Systems (pp. 58-61). ACM.
    • Rahimi, A., Benini, L., & Gupta, R. K. (2014). Analysis of Cross-layer Vulnerability to Variations: An Adaptive Instruction-level to Task-level Approach. UCSD Technical Report, CS2014-1004.
    • Beneventi, F., Bartolini, A., & Benini, L. (2013, September). On-line thermal emulation: How to speed-up your thermal controller design. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013 23rd International Workshop on (pp. 99-106). IEEE.
    • Bortolotti, D., Bartolini, A., Weis, C., Rossi, D., & Benini, L. (2014, March). Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 (pp. 1-6). IEEE.
    • Rahimi, A., Cesarini, D., Marongiu, A., Gupta, R. K., & Benini, L. (2014). Improving resilience to timing errors by exposing variability effects to software in tightly-coupled processor clusters. Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, 4(2), 216-229.
    • Papagiannopoulou, D., Moreshet, T., Marongiu, A., Benini, L., Herlihy, M., & Iris Bahar, R. (2014, July). Speculative synchronization for coherence-free embedded NUMA architectures. In Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 2014 International Conference on (pp. 99-106). IEEE.
    • Bortolotti, D., Mamaghanian, H., Bartolini, A., Ashouei, M., Stuijt, J., Atienza, D., … & Benini, L. (2014, August). Approximate compressed sensing: ultra-low power biosignal processing via aggressive voltage scaling on a hybrid memory multi-core processor. In Proceedings of the 2014 international symposium on Low power electronics and design (pp. 45-50). ACM.
    • Bortolotti, D., Mangia, M., Bartolini, A., Rovatti, R., Setti, G., & Benini, L. (2014). Rakeness-based Compressed Sensing on Ultra-Low Power Multi-Core Biomedical Processors. Proceedings of DASIP.
    • Kanoun, K., Ruggiero, M., Atienza, D., & Van Der Schaar, M. (2014, July). Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing. In VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on (pp. 468-473). IEEE.
    • Burgio, Paolo, et al. “Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters.” Proceedings of the conference on Design, Automation & Test in Europe. European Design and Automation Association, 2014.
    • Rahimi, A., Cesarini, D., Marongiu, A., Gupta, R. K., & Benini, L. (2015). Task Scheduling Strategies to Mitigate Hardware Variability in Embedded Shared Memory Clusters.
    • Bortolotti, D., Bartolini, A., & Benini, L. (2014). An ultra-low power resilient multi-core architecture with static and dynamic tolerance to ambient temperature-induced variability. Microprocessors and Microsystems, 38(8), 776-787.
    • Balboni, M., & Bertozzi, D. (2015, July). NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators. In High Performance Computing & Simulation (HPCS), 2015 International Conference on (pp. 643-645). IEEE.
    • Burgio, P., Danilo, R., Marongiu, A., Coussy, P., & Benini, L. (2014, March). A tightly-coupled Hardware Controller to improve scalability and programmability of shared-memory heterogeneous clusters. In Proceedings of the conference on Design, Automation & Test in Europe (p. 25). European Design and Automation Association.
    • Horváth, Péter, Gábor Hosszú, and Ferenc Kovács. “A proposed synthesis method for Application-Specific Instruction Set Processors.” Microelectronics Journal 46.3 (2015): 237-247.
    • Burgio, P., Marongiu, A., Coussy, P., & Benini, L. (2014, August). A HLS-based toolflow to design next-generation heterogeneous many-core platforms with shared memory. In Embedded and Ubiquitous Computing (EUC), 2014 12th IEEE International Conference on (pp. 130-137). IEEE.
    • Papagiannopoulou, D., Marongiu, A., Moreshet, T., Benini, L., Herlihy, M., & Bahar, I. (2015, May). Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI (pp. 9-14). ACM.
    • Carle, T., Papagiannopoulou, D., Bahar, I., Herlihy, M., & Moreshet, T. (2015, July). A transaction-friendly dynamic memory manager for embedded multicore systems. In Proceedings of the 7th Workshop on Theory of Transactional Memory (WTTM).
    • Gomez, A., Pinto, C., Bartolini, A., Rossi, D., Benini, L., Fatemi, H., & de Gyvez, J. P. (2015, March). Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (pp. 269-272). EDA Consortium.
    • Bortolotti, D., Mangia, M., Bartolini, A., Rovatti, R., Setti, G., & Benini, L. (2015, March). An ultra-low power dual-mode ECG monitor for healthcare and wellness. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (pp. 1611-1616). EDA Consortium.
    • Tagliavini, G., Rossi, D., Benini, L., & Marongiu, A. (2015, July). Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. In VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium on (pp. 280-285). IEEE.