Several Chip-Multiprocessor designs today leverage tightly-coupled computing clusters as a building block. These clusters consist of a fairly large number N of simple cores, featuring fast communication through a shared multibanked L1 data memory and 1 Instruction-Per-Cycle (IPC) per core.

We developed a cycle-accurate model of the tightly coupled cluster with several configurable architectural parameters for exploration, plus a programming environment targeted at efficient data-parallel computing.


We are currently releasing a BETA version of the Virtual Platform.

Main features of the release:

  • Hardware
    • Single-Cluster architecture
      • up to 16 ARMv6 cores
      • multi-banked, multi-ported Tigthly Coupled Data Memory (TCDM)
      • fast logarithmic interconnect for cluster communication
      • Hardware Synchronizer (HWS) module to enable core synchronization
        (also used by the libgomp runtime)
      • Cycle-accurate DRAM memory controller as external main memory
      • DMA Engine per cluster
  • Software
    • custom lightweight OpenMP runtime (based on OpenMP v2.5)
    • OpenMP applications
    • bare simple example applications

The future release of VirtualSoC, we are currently working on, will feature:

  • Hardware
    • Multi-cluster architecture with global NoC (mesh topology)
    • HWPU (Hardware Processing Units) custom accelerators integrated in the cluster
    • Integration of QEMU (host, with linux driver) and VirtualSoC as many-core accelerator
  • Software
    • OTF tracing in application (integrated in library runtime)
    • custom lightweight OpenMP runtime (OpenMP v3.0 – tasking support)
    • benchmark suite (EEMBCMiBench benchmarks)

The source code of VirtualSoC is available (BETA version) in the download section.