Publications

2016

  • Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms, F. Conti, D. Palossi, A. Marongiu, D. Rossi, L. Benini, DATE, 2016 (to appear)
  • High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme, Y. Popoff, F. Scheidegger, M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, DATE, 2016 (to appear)
  • A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster, M. Gautschi, M. Schaffner, F. K. Gürkaynak, L. Benini, ISSCC, 2016

2015

  • A Ultra-Low-Energy Convolution Engine for Fast Brain-inspired Vision in Multicore Clusters, F. Conti, L. Benini, DATE, 2015, paper
  • Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs, P. Vogel, A. Marongiu, L. Benini, CODES+ISSS, 2015, paper
  • Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters, I. Loi, D. Rossi, G. Haugou, M. Gautschi, L. Benini, ACM Computing Frontiers, 2015, paper
  • PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision, F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, Journal of Signal Processing Systems, October 2015, paper
  • A ?1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology, D. Rossi, A. Pullini, M. Gautschi, I. Loi, F.K. Gurkaynak, P. Flatresse, L. Benini, S3S, October 2015, paper
  • A 60 GOPS/W, ?1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology, D. Rossi, A. Pullini, I. Loi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, Solid-State Electronics, 2016, paper
  • PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications, D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, L. Benini, HOT Chips, 2015, slides
  • Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores, M. Gautschi, A. Traber, A. Pullini, L. Benini, M. Scandale, A. Di Federico, M. Beretta, G. Agosta, VLSI-SoC, 2015, paper

2014

  • Energy-efficient vision on the PULP platform for ultra-low power parallel computing, F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, SiPS, 2014, paper
  • Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters, D. Rossi, I. Loi, G. Haugou, L. Benini, ACM Computing Frontiers, 2014, paper
  • Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory, M. Gautschi, D. Rossi, L. Benini, GLSVLSI, 2014, paper
  • Energy efficient parallel computing on the PULP platform with support for OpenMP, D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, A. Marongiu, IEEEI, 2014, paper

Presentations

[table width=”700″ colwidth=”400|150|100|50″ colalign=”left|left|center”]
Title,Author,Place/Year

Sub-pJ-Operation Scalable Computing: The PULP Experience, Luca Benini, 2016

PULPino: A small single-core RISC-V SoC, Andreas Traber, RISC-V Workshop 2016 (Poster)

PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications, Davide Rossi, HotChips 2015 (Video)

PULPino: A RISC-V based single-core system, Andreas Traber, ORCONF 2015 (Video)

PULP: OpenRISC-based ultra-low power parallel platform, Francesco Conti, ORCONF 2015 (Video)

[/table]

 

 

 

 

 

 

 

Leave a Comment

Your email address will not be published. Required fields are marked *