PULP – An Open Parallel Ultra-Low-Power Processing-Platform

The PULP-project is a joint project between the Integrated Systems laboratory (IIS) of ETH Zurich (IIS) and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.

The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meetĀ  the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.

The PULP architecture is tuned for efficient near-threshold operation and includes technology-aware architectural optimizations targeting 28nm UTBB FD-SOI technology. With respect to traditional bulk technology, UTBB FD-SOI enables an extended range of supply voltage and body bias and a better electrostatic control, which provides 85mV/V of threshold voltage/body bias voltage modulation. PULP exploits these capabilities by supporting fine-grained, ultra-dynamic, and state-retentive leakage management of processors. The high-performance (flip-well) flavor of the technology operates at frequencies in theĀ  multi-GHz region, and allows to apply aggressive (up to +2V) forward body-biasing (FBB) to major operating frequency boost; on the other hand, the conventional-well flavor features low-leakage transistors where reverse body-biasing (RBB) up to -3V and forward body-biasing (FBB) up to (VDD/2 + 300 mV) can be applied.

Both technology flavors have been investigated for the implementations of the PULP platform. Being low-leakage, and supporting both RBB and FBB, the conventional-well technology brings more flexibility with respect to the flip-well flavor and appears more suited for the IoT class of applications.


PULPino – A Small Single-Core System Based on PULP:

PULPino is an open-source microcontroller like system, based on a small 32-bit RISC-V core that was developed at ETH Zurich. The core has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and partial support for the multiplication instruction set extension (RV32M). It implements our non-standard extensions for hardware loops, post-incrementing load and store instructions, ALU and MAC operations. To allow embedded operating systems such as FreeRTOS to run, a subset of the privileged specification is supported. When the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and wakes up the core in case an event/interrupt arrives.

The PULPino platform is available for RTL simulation, FPGA and the first ASIC (called Imperio) has been taped out in January 2016. It has full debug support on all targets. In addition we support extended profiling with source code annotated execution times through KCacheGrind in RTL simulations.

PULPino is based on IP blocks from the PULP project.
See also:


This project is supported, in parts, by EU FP7 ERC Project MULTITHERMAN (GA no. 291125).

Related Available Student Projects (ETHZ)

PULP Chips


  • Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
  • Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
  • Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
  • Honey Bunny PULP platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.


  • Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 Kbyte memory (65nm)
  • Artemis 4 core PULP system including FPU (65nm).
  • Hecate 4 core PULP system with 2 shared FPUs (65nm).
  • Selene 4 core PULP system with 1 shared FPU using a logarithmic number system (65nm).
  • Diana 4 core PULP system with FPUs designed using approximate computing techniques (65nm).


  • Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter (130nm)


  • Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP (180nm).
  • Sir10us A cryptographic application that uses the Or10n processor developed for PULP (180nm).
  • Sid Large PULP chip with in-exact accelerators, LL version
  • Diego Large PULP chip with in-exact accelerators, LVT version
  • Manny Large PULP chip with in-exact accelerators, sub-threshold version



1 Comment

  1. Mohammed Al-Daloo

    Dear sir
    I am really interesting in your project.
    I have a research on Design interconnects in ultra-low power digital system. what have I been done for now design a driver to 10mm interconnect with subthreshold voltage supply using cadence (spectre) tool kit. I wonder if your platform could support my work to apply it on.


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